1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for fabricating a multi-layered dielectric layer for reducing parasitic capacitance generated between conductive patterns which exist on the same layer or between conductive layers formed in different levels.
2. Description of the Related Art
As the level of integration and speed of semiconductor devices increases, a design rule is reduced and a multi-layered metal wiring layer is required. As a result, the distance between metal wiring layers on the same layer is gradually reduced and the widths of the metal wiring layers and the distance between the metal wiring layers are reduced. As the width of metal wiring layers is reduced, the resistance thereof increases proportionally. As the distance between the metal layers is reduced, a parasitic capacitance between the metal wiring layers increases. The increase of the resistance or the parasitic capacitance may significantly reduce the speed of the semiconductor device.
Accordingly, parasitic resistance R and capacitance C components which exist between metal wiring layers adjacent to each other on the same layer or wiring layers vertically adjacent to each other, are most important.
In a metal wiring system, the parasitic resistance and capacitance elements deteriorate the electrical performance of a device due to the RC-induced propagation delays. Also, the parasitic resistance and capacitance elements which exist between the wiring layers increase the overall chip power dissipation and increase the amount of signal cross talk. Therefore, in an ultra-large-scale integrated semiconductor device, it is very important to develop suitable low-RC multi-level interconnect technologies.
It is essential to use an intermetal dielectric film having a low dielectric constant in order to form a high performance multi-level interconnect structure having low RC.
Research for using methyl silsesquioxane (MSQ), which is a spin-on-glass (SOG) insulating material, as a material which can be used as an intermetal dielectric film which can realize a low dielectric constant, is proceeding.
FIGS. 1A and 1B show the basic structures of MSQ and a flowable oxide (FOx), respectively. As shown in FIG. 1A, the basic structure of MSQ is a cage structure formed of Sixe2x80x94Oxe2x80x94Si bonds. The basic structure of MSQ is similar to the basic structure of FOx. FOx is a currently used insulating material and has a dielectric constant no less than 3.0. Meanwhile, MSQ can show a relatively low dielectric constant of 2.5 through 3.0 according to the amount of methyl group (xe2x80x94CH3) included in the basic structure thereof. MSQ has a low dielectric constant because the density in the MSQ layer is low, and a Sixe2x80x94CH3 bond has a strong covalent bonding characteristic and has low hygroscopicity since MSQ has a cage structure like that of FOx.
Therefore, if MSQ is used for forming the interlayer dielectric film of the semiconductor device, it is very advantageous since it is possible to use process conditions for FOx already set-up in the currently used semiconductor manufacturing equipment with slight change.
However, while the edge of the polygon structure of FOx is terminated by a Sixe2x80x94H bond, the edge of the polygon structure of MSQ is terminated by Sixe2x80x94CH3 and Sixe2x80x94H bonds. Therefore, when MSQ is applied to the intermetal dielectric film, a steric hindrance between the MSQ layer and an upper dielectric layer deposited on the MSQ layer is very large due to relatively bulky xe2x80x94CH3 group on the surface of the MSQ layer. As a result, bonding power between the MSQ layer and the upper dielectric layer is weakened. Accordingly, adhesion between, the two layers is weakened.
When the upper dielectric layer is planarized by, for example, a chemical mechanical polishing (CMP) method or a conductive layer is polished for forming a via contact plug in a successive process in a state where the adhesion between the MSQ layer and the upper dielectric layer is weakened, a peeling off phenomenon where the upper dielectric layer is lifted and taken off from the MSQ layer occurs. This is because the bonding power between the MSQ layer and the upper dielectric layer cannot withstand the physical force transmitted from the surface of a wafer to an interface between the MSQ layer and the upper dielectric layer during the CMP process.
The above-mentioned problem is not restricted to MSQ but occurs in other insulating layers containing the Sixe2x80x94CH3 bond such as silicon oxycarbide (SiOC).
When the peeling off phenomenon of the upper dielectric layer is serious, the upper dielectric layer is taken off during the process of planarizing the upper dielectric layer. As a result, a case may result where upper dielectric layers are removed by the polishing process, and a lower conductive layer is exposed.
To solve the above problem and one or more of the problems due to limitations and disadvantages of the related art, it is an object of the present invention to provide a multi-layered dielectric layer including an insulating layer which has a Sixe2x80x94CH3 bond and has excellent bonding power with an upper dielectric layer.
It is another object of the present invention to provide a method for fabricating a multi-layered dielectric layer including an insulating layer having a Sixe2x80x94CH3 bond with enhanced bonding power, by which it is possible to improve adhesion thereof to an upper dielectric layer formed on the insulating layer.
To achieve the first object, there is provided a multi-layered dielectric layer according to an aspect of the present invention, including a first insulating layer formed on conductive patterns on a semiconductor substrate, the first insulating layer having Sixe2x80x94CH3 bonds therein, an adhesion surface formed to be exposed on the upper surface of the first insulating layer, wherein the adhesion surface is part of the first insulating layer and has a carbon component of smaller quantity than the remaining part of the first insulating layer, and a second insulating layer formed on the adhesion surface of the first insulating layer so that a dipolexe2x80x94dipole interaction occurs between the adhesion surface and the second insulating layer.
To achieve the first object, there is provided a multi-layered dielectric layer according to another aspect of the present invention, including a first insulating layer formed on conductive patterns on a semiconductor substrate, the first insulating layer having Sixe2x80x94CH3 bonds therein, a buffer layer formed on the first insulating layer, wherein the buffer layer does not include the Sixe2x80x94CH3 bond therein, and is formed so that a dipolexe2x80x94dipole interaction occurs between the first insulating layer and the buffer layer, and a second insulating layer formed on the buffer layer.
The first insulating layer is formed of methyl silsesquioxane (MSQ) or silicon oxycarbide (SiOC).
The buffer layer is preferably formed of undoped silicate glass (USG).
To achieve the second object, there is provided a method for forming a multi-layered dielectric layer according to an aspect of the present invention. In the method for forming the multi-layered dielectric layer, a first insulating layer having Sixe2x80x94CH3 bonds is formed on conductive patterns on a semiconductor substrate. An adhesion surface including a carbon component of less quantity than the first insulating layer is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. A second insulating layer is formed on the adhesion surface so that a dipolexe2x80x94dipole interaction occurs between the adhesion surface and the second insulating layer.
O2, N2O or NH3/N2 plasma is used to treat the first insulating layer.
To achieve the second object, there is provided a method of forming a multi-layered dielectric layer according to another aspect of the present invention. In the method for forming the multi-layered dielectric layer, a first insulating layer including a Sixe2x80x94CH3 bond is formed on conductive patterns on a semiconductor substrate. A buffer layer is formed on the first insulating layer so that a dipolexe2x80x94dipole interaction occurs between the first insulating layer and the buffer layer, wherein the buffer layer does not have Sixe2x80x94CH3 bonds therein. A second insulating layer is formed on the buffer layer.
The buffer layer is preferably formed of undoped silicate glass (USG) to a thickness of 50 xc3x85 through 1000 xc3x85.
According to the present invention, it is possible to reduce RC delays which can be generated in a metal wiring system, by using material having a low dielectric constant for fabricating an intermetal dielectric film. Also, by fabricating a layer having a low dielectric constant that includes the Sixe2x80x94CH3 bond, it is possible to significantly improve adhesion between the layer having the low dielectric constant and an upper dielectric layer by removing the Sixe2x80x94CH3 bond on the surface of the layer having the low dielectric constant.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.